And here’s the equivalent of the cheap clone. Yes, delete it Cancel. I was supposed to work on getting the SiI up and running , but UPS delivered a nice package today: What remains is the question about why the cheap clone doesn’t work. For the cheap clone, the spacing is huge: The most important signal here is TCK, in yellow. The suffix is really different, with 6 clock clocks but also a fast clock group in between.
|Date Added:||4 February 2008|
|File Size:||60.87 Mb|
|Operating Systems:||Windows NT/2000/XP/2003/2003/7/8/10 MacOS 10/X|
|Price:||Free* [*Free Regsitration Required]|
In the middle there are 16 groups with fast clock cycles each group is itself 8 clock cycles. There are 3 major sections: It’s not that it’s broken: The set of signals below that is a slightly zoomed in version of the one above.
For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan DR or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of terasci scan data register. The cheap clone was never able to get reliable contact.
USB Blaster Cable
When you zoom in on the slow clock cycles, you can measure a TCK frequency of kHz: It looks like the cheap altea is able to squeeze out bits really fast, but there’s quite a bit of software overhead in processing the next byte in the USB packet. My money is on the clock speed: While the Terasic was rock solid in its communication with the Color3 board.
The Terasic doesn’t have that problem: What remains is the blasteg about why the cheap clone doesn’t work. And at the end you have a suffix with 2 slow clock cycles.
If we ignore for a second that the cheap clone doesn’t work on this particular board, the biggest consequence of the chapeau clone is that bulk transfers are much aaltera We see a similar pattern, but interestingly enough, it’s not the same. In the middle we have the expected 16 fast clock groups. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today: In addition, there are roughly 3 idle cycles between a fast clock group.
Terasic USB Blaster Cable For Altera – % compatible with Altera USB blaster download cable
About Us Contact Hackaday. Zooming in on the slow clocks, we see a clock frequency of kHz. For the cheap clone, the spacing is huge: A fast clock group sets the clock at 12MHz instead of 6MHz. This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today:.
Terasic vs Cheap Clone USB Blaster | Details |
The suffix is really different, with 6 clock clocks but also a fast clock group in between. For the overview, look at the upper set. But the cheap clone runs TCK at exactly double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable. And here’s the equivalent of the cheap clone. Yes, delete it Cancel. Meanwhile, during a fast clock group, the clock toggles at 6MHz.
A really interesting difference is in the spacing between fast clock groups: All processing is teraslc with a simply state machine. ush
Terasic vs Cheap Clone USB Blaster
We have a prefix with 8 slow clocks, but in between the second and the third slow clock, there’s a signal fast clock group. Sign up Already a member? As I wrote earlierthe biggest issue with the cheap clone is that it vlaster work on my eeColor Color3 board.
The most important signal here is TCK, in yellow.